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| Freescale Semiconductor, Inc. Semiconductor Products Sector Order Number: MPC603E7TEC/D Rev. 4, 5/2000 Freescale Semiconductor, Inc... Technical Data PowerPC 603e RISC Microprocessor Family: PID7t-603e Hardware Specications The PowerPC 603e microprocessor is an implementation of the PowerPC family of reduced instruction set computing (RISC) microprocessors. In this document, the term O603eO is used as an abbreviation for the PowerPC 603e microprocessor. The PowerPC 603e microprocessors are available from Motorola as MPC603e. The 603e is implemented in several semiconductor fabrication processes. Different processes may require different supply voltages and may have other electrical differences but will have the same functionality. As a technical designator to distinguish between 603e implementations in various processes, a prex composed of the processor version register (PVR) value and a process identier (PID) is assigned to the various implementations as shown below: Table 1PowerPC 603e Microprocessors from Motorola Technical Designator PID6-603e PID7v-603e PID7t-603e Process 0.5 m CMOS, 4LM 0.35 m CMOS, 5LM 0.29 m CMOS, 5LM Core Voltage 3.3 V 2.5 V 2.5 V I/O Voltage 3.3 V 3.3 V 3.3 V 5-Volt Tolerant Yes Yes Yes Part Number MPC603E XPC603P (end-of-life) MPC603R This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc., 2000. All rights reserved. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Overview This document describes the pertinent physical characteristics of the PID7t-603e from Motorola. For functional characteristics of the 603e, refer to the PowerPC 603e RISC Microprocessor UserOs Manual. This document contains the following topics: Topic Page Freescale Semiconductor, Inc... Section 1.1, OOverviewO Section 1.2, OFeaturesO Section 1.3, OGeneral ParametersO Section 1.4, OElectrical and Thermal CharacteristicsO Section 1.5, OPin AssignmentsO Section 1.6, OPinout ListingsO Section 1.7, OPackage DescriptionsO Section 1.8, OSystem Design InformationO Section 1.9, OOrdering InformationO To locate any published errata or updates for this document, refer to the website at http://www.motorola.com/semiconductors. 2 3 4 5 15 16 18 23 33 1.1 Overview This section describes the features of the 603e and describes briey how those units interact. The 603e is a low-power implementation of the PowerPC microprocessor family of reduced instruction set computing (RISC) microprocessors. The 603e implements the 32-bit portion of the PowerPC architecture specication, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and oating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management mode that causes the functional units in the 603e to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance; however, the 603e makes completion appear sequential. The 603e integrates ve execution unitsNan integer unit (IU), a oating-point unit (FPU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute ve instructions in parallel and the use of simple instructions with rapid execution times yield high efciency and throughput for 603e-based systems. Most integer instructions execute in one clock cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle. The 603e provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The 603e also 2 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Features supports block address translation through the use of two independent instruction and data block address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes priority. The 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603e interface protocol allows multiple masters to compete for system resources through a central external arbiter. The 603e provides a three-state coherency protocol that supports the exclusive, modied, and invalid cache states. This protocol is a compatible subset of the MESI (modied/exclusive/shared/invalid) four-state protocol and operates coherently in systems that contain four-state caches. The 603e supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/O. The 603e uses an advanced, 2.5/3.3-V CMOS process technology and maintains full interface compatibility with TTL devices. The PID7t-603e is offered in both PBGA and CBGA packages. The CBGA package supports speed bins of 200 MHz, 266 MHz, and 300 MHz. The PBGA package is a pin-compatible drop in replacement for the CBGA; however this package only supports speeds up to 200 MHz. Freescale Semiconductor, Inc... 1.2 Features This section summarizes features of the 603eOs implementation of the PowerPC architecture. Major features of the 603e are as follows: High-performance, superscalar microprocessor N As many as three instructions issued and retired per clock N As many as ve instructions in execution per clock N Single-cycle execution for most instructions N Pipelined FPU for all single-precision and most double-precision operations Five independent execution units and two register les N BPU featuring static branch prediction N A 32-bit IU N Fully IEEE 754-compliant FPU for both single- and double-precision operations N LSU for data transfer between data cache and GPRs and FPRs N SRU that executes condition register (CR), special-purpose register (SPR) instructions, and integer add/compare instructions N Thirty-two GPRs for integer operands N Thirty-two FPRs for single- or double-precision operands High instruction and data throughput N Zero-cycle branch capability (branch folding) N Programmable static branch prediction on unresolved conditional branches N Instruction fetch unit capable of fetching two instructions per clock from the instruction cache N A six-entry instruction queue that provides lookahead capability N Independent pipelines with feed-forwarding that reduces data dependencies in hardware N 16-Kbyte data cacheNfour-way set-associative, physically addressed; LRU replacement algorithm PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. General Parameters N 16-Kbyte instruction cacheNfour-way set-associative, physically addressed; LRU replacement algorithm N Cache write-back or write-through operation programmable on a per page or per block basis N BPU that performs CR lookahead operations N Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte segment size N A 64-entry, two-way set-associative ITLB N A 64-entry, two-way set-associative DTLB N Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks N Software table search operations and updates supported through fast trap mechanism N 52-bit virtual address; 32-bit physical address Freescale Semiconductor, Inc... Facilities for enhanced system performance N A 32- or 64-bit split-transaction external data bus with burst transfers N Support for one-level address pipelining and out-of-order bus transactions Integrated power management N Low-power 2.5/3.3-volt design N Internal processor/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, and 6:1 ratios N Three power saving modes: doze, nap, and sleep N Automatic dynamic power reduction when internal functional units are idle In-system testability and debugging features through JTAG boundary-scan capability 1.3 General Parameters The following list provides a summary of the general parameters of the PID7t-603e: Technology Die size Transistor count Logic design Package Core power supply I/O power supply 0.29 m CMOS, ve-layer metal 5.65 mm x 7.7 mm (44 mm2) 2.6 million Fully-static 255 ceramic ball grid array (CBGA) or 225 thin map plastic ball grid array (PBGA) 2.5 5% V dc 3.3 5% V dc 4 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical and Thermal Characteristics 1.4 Electrical and Thermal Characteristics This section provides the AC and DC electrical specications and thermal characteristics for the PID7t-603e. 1.4.1 DC Electrical Characteristics The tables in this section describe the PID7t-603e DC electrical characteristics. Table 2 provides the absolute maximum ratings. Table 2. Absolute Maximum Ratings Characteristic Core supply voltage Vdd AVdd OVdd Vin Tstg Symbol Value -0.3 to 2.75 -0.3 to 2.75 -0.3 to 3.6 -0.3 to 5.5 -55 to 150 Unit V V V V C Freescale Semiconductor, Inc... PLL supply voltage I/O supply voltage Input voltage Storage temperature range Notes: 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: Vin must not exceed OVdd by more than 2.5 V at any time, including during power-on reset. 3. Caution: OVdd must not exceed Vdd/AVdd by more than 1.2 V at any time, including during power-on reset. 4. Caution: Vdd/AVdd must not exceed OVdd by more than 0.4 V at any time, including during power-on reset. Table 3 provides the recommended operating conditions for the PID7t-603e. Table 3. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage I/O supply voltage Input voltage Die-junction temperature Vdd AVdd OVdd Vin Tj Symbol Value 2.375 to 2.625 2.375 to 2.625 3.135 to 3.465 GND to 5.5 0 to 105 Unit V V V V C Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. Electrical and Thermal Characteristics Table 4 provides the package thermal characteristics for the PID7t-603e. Table 4. Package Thermal Characteristics Characteristic Package die junction-to-case thermal resistance (typical) Package die junction-to-ball thermal resistance (typical) Symbol qJC qJB Value CBGA 0.095 3.5 Value PBGA 8.0 13 Rating C/W C/W Note: Refer to Section 1.8, "System Design Information," for more details about thermal management. Table 5 provides the DC electrical characteristics for the PID7t-603e. Table 5. DC Electrical Specifications Freescale Semiconductor, Inc... Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C Characteristic Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage Input leakage current, Vin = 3.465 V Vin = 5.5 V Hi-Z (off-state) leakage current, Vin = 3.465 V Vin = 5.5 V Output high voltage, IOH = 7 mA Output low voltage, IOL = 7 mA Capacitance, Vin = 0 V, f = 1 MHz (excludes TS, ABB, DBB, and ARTRY) Symbol VIH VIL CVIH CVIL Iin Iin ITSI ITSI VOH VOL Cin Min 2.0 GND 2.4 GND -- -- -- -- 2.4 -- -- Max 5.5 0.8 5.5 0.4 30 300 30 300 -- 0.4 10.0 V V V V Unit Notes A A A A V V pF 1,2 1,2 1,2 1,2 3 Capacitance, Vin = 0 V, f = 1 MHz (for TS, ABB, DBB, and ARTRY) Cin Notes: -- 15.0 pF 3 1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals). 2. The leakage is measured for nominal OVdd and Vdd or both OVdd and Vdd must vary in the same direction (for example, both OVdd and Vdd vary by either +5% or -5%). 3. Capacitance is periodically sampled rather than 100% tested. 6 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical and Thermal Characteristics Table 6 provides the power consumption for the PID7t-603e. Table 6. Power Consumption Processor (CPU) Frequency 100 MHz Full-On Mode (DPM Enabled) Typical Maximum Doze Mode 1.1 1.6 1.6 2.4 2.1 3.2 2.5 4.0 3.0 4.6 3.5 5.3 4.0 6.0 W W 133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz Unit Freescale Semiconductor, Inc... Typical Nap Mode Typical Sleep Mode Typical 0.55 .7 .9 1.1 1.3 1.5 1.8 W 50 60 75 85 100 120 130 mW 45 50 55 65 75 90 100 mW Sleep ModeNPLL Disabled Typical 40 40 40 40 40 40 40 mW Sleep ModeNPLL and SYSCLK Disabled Typical Maximum Notes: 1. These values apply for all valid PLL_CFG[0-3] settings and do not include output driver power (OVdd) or analog supply power (AVdd). OVdd power is system dependent but is typically 10% of Vdd. Worst-case AVdd = 15 mW. 2. Typical power is an average value measured at Vdd = AVdd = 2.5 V, OVdd = 3.3V, in a system executing typical applications and benchmark sequences. 3. Maximum power is measured at 2.625 V using a worst-case instruction mix. 15 25 15 25 15 25 15 25 15 25 15 80 15 100 mW mW 1.4.2 AC Electrical Characteristics This section provides the AC electrical characteristics for the PID7t-603e. These specications are for 200, 266 and 300 MHz processor speed grades. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[03] signals. All timings are specied respective to the rising edge of SYSCLK. PLL_CFG signals should be set prior to power up and not altered afterwards. PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc. Electrical and Thermal Characteristics 1.4.2.1 Clock AC Specications Table 7 provides the clock AC timing specications as dened in Figure 1. After fabrication, parts are sorted by maximum processor core frequency as shown in Section 1.4.2.1, OClock AC Specications,O and tested for conformance to the AC specications for that frequency. Parts are sold by maximum processor core frequency; see Section 1.9, OOrdering Information.O Table 7. Clock AC Timing Specifications Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C Num Characteristic 200 MHz PBGA Min Max 200 200 MHz CBGA Min 80 266 MHz CBGA Min 150 300 MHz CBGA Min 180 Unit Notes Max 200 Max 266 Max 300 MHz 1,6 Freescale Semiconductor, Inc... Processor frequency VCO frequency SYSCLK frequency 1 SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle measured at 1.4 V SYSCLK jitter PID7t internal PLL-relock time 100 300 400 300 400 300 532 360 600 MHz 1 25 66.67 25 66.67 25 75 33.3 75 MHz 1 13.3 40 13.3 40 13.3 40 13.3 30 ns 2,3 -- 2.0 -- 2.0 -- 2.0 -- 2.0 ns 2 4 40.0 60.0 40.0 60.0 40.0 60.0 40.0 60.0 % 3 -- -- 150 100 -- -- 150 100 -- -- 150 100 -- -- 150 100 ps ms 4 3,5 Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description in Section 1.8, "System Design Information," for valid PLL_CFG[0-3] settings. 2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V. 3. Timing is guaranteed by design and characterization, and is not tested. 4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term combined) must be under 150 ps to guarantee the input/output timing of Section 1.4.2.2, "Input AC Specifications," and Section 1.4.2.3, "Output AC Specifications." 5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100 ms) during the power-on reset sequence. 6. Operation below 150 MHz is supported only by PLL_CFG[0-3] = 0b0101. Refer to Section 1.8.1, "PLL Configuration" for additional information. 8 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical and Thermal Characteristics Figure 1 provides the SYSCLK input timing diagram. 1 4 4 CVih VM VM VM CVil 2 3 SYSCLK VM = Midpoint Voltage (1.4 V) Figure 1. SYSCLK Input Timing Diagram Freescale Semiconductor, Inc... 1.4.2.2 Input AC Specications Table 8 provides the input AC timing specications for the PID7t-603e as dened in Figure 2 and Figure 3. Table 8. Input AC Timing Specifications1 Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C 200, 266, 300 MHz Num Characteristic Min 10a 10b 10c Address/data/transfer attribute inputs valid to SYSCLK (input setup) All other inputs valid to SYSCLK (input setup) Mode select inputs valid to HRESET (input setup) (for DRTRY, QACK and TLBISYNC) SYSCLK to address/data/transfer attribute inputs invalid (input hold) SYSCLK to all other inputs invalid (input hold) HRESET to mode select inputs invalid (input hold) (for DRTRY, QACK, and TLBISYNC) 2.5 3.5 8 Max -- -- -- ns ns tsysclk ns ns ns 2 3 4, 5, 6, 7 Unit Notes 11a 11b 11c 1.0 1.0 0 -- -- -- 2 3 4, 6, 7 Notes: 1. Input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the rising edge of the input SYSCLK. Input and output timings are measured at the pin. 2. Address/data/transfer attribute input signals are composed of the following--A[0-31], AP[0-3], TT[0-4], TC[0-1], TBST, TSIZ[0-2], GBL, DH[0-31], DL[0-31], DP[0-7]. 3. All other input signals are composed of the following--TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC. 4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3). 5. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. These values are guaranteed by design, and are not tested. 7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 9 Freescale Semiconductor, Inc. Electrical and Thermal Characteristics Figure 2 provides the input timing diagram for the PID7t-603e. SYSCLK 10a 10b VM 11a 11b ALL INPUTS VM = Midpoint Voltage (1.4 V) Freescale Semiconductor, Inc... Figure 2. Input Timing Diagram Figure 3 provides the mode select input timing diagram for the PID7t-603e. HRESET 10c VM 11c MODE PINS VM = Midpoint Voltage (1.4 V) Figure 3. Mode Select Input Timing Diagram 1.4.2.3 Output AC Specications Table 9 provides the output AC timing specications for the PID7t-603e as dened in Figure 4. Table 9. Output AC Timing Specifications1 Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5%, GND = 0 V dc, 0 Tj 105 C, CL = 50 pF (unless otherwise noted) 200, 266, 300 MHz Num Characteristic Min 12 13a SYSCLK to output driven (output enable time) SYSCLK to output valid (5.5 V to 0.8 V--TS, ABB, ARTRY, DBB) SYSCLK to output valid (TS, ABB, ARTRY, DBB) SYSCLK to output valid (5.5 V to 0.8 V--all except TS, ABB, ARTRY, DBB) 1.0 -- Max -- 9.0 ns ns 3 Unit Notes 13b 14a -- -- 8.0 11.0 ns ns 5 3 10 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical and Thermal Characteristics Table 9. Output AC Timing Specifications1 (Continued) Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5%, GND = 0 V dc, 0 Tj 105 C, CL = 50 pF (unless otherwise noted) 200, 266, 300 MHz Num Characteristic Min 14b SYSCLK to output valid (all except TS, ABB, ARTRY, DBB) SYSCLK to output invalid (output hold) SYSCLK to output high impedance (all except ARTRY, ABB, DBB) SYSCLK to ABB, DBB, high impedance after precharge SYSCLK to ARTRY high impedance before precharge SYSCLK to ARTRY precharge enable -- Max 9.0 ns 5 Unit Notes 15 16 1.0 -- -- 8.0 ns ns 2 Freescale Semiconductor, Inc... 17 -- 1.0 tsysclk ns 4, 6 18 -- 7.5 19 0.2 * tsysclk + 1.0 -- -- -- ns 2, 4, 7 20 21 Maximum delay to ARTRY precharge SYSCLK to ARTRY high impedance after precharge 1.0 2.0 tsysclk tsysclk 4, 7 5,7 Notes: 1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 4). 2. This minimum parameter assumes CL = 0 pF. 3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels). 4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 5. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V. 6. Nominal precharge width for ABB and DBB is 0.5 tsysclk. 7. Nominal precharge width for ARTRY is 1.0 tsysclk. PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 11 Freescale Semiconductor, Inc. Electrical and Thermal Characteristics Figure 4 provides the output timing diagram for the PID7t-603e. SYSCLK VM 14 15 12 16 VM VM ALL OUTPUTS (Except TS, ABB, DBB, ARTRY) 13 13 15 16 TS Freescale Semiconductor, Inc... 17 ABB, DBB 21 20 19 18 ARTRY VM = Midpoint Voltage (1.4 V) Figure 4. Output Timing Diagram 12 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Electrical and Thermal Characteristics 1.4.3 JTAG AC Timing Specications Table 10 provides the JTAG AC timing specications as dened in Figure 5, Figure 6, Figure 7 and Figure 8. Table 10. JTAG AC Timing Specifications Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5%, GND = 0 V dc, 0 Tj 105 C, CL = 50 pF Num Characteristic TCK frequency of operation 0 Min Max 16 -- -- 3 -- -- -- -- 25 24 -- -- 24 15 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 1 2 TCK cycle time TCK clock pulse width measured at 1.4 V TCK rise and fall times TRST setup time to TCK rising edge TRST assert time Boundary scan input data setup time Boundary scan input data hold time TCK to output data valid TCK to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid TCK to TDO high impedance 62.5 25 0 13 40 6 27 4 3 0 25 4 3 Freescale Semiconductor, Inc... 3 4 5 6 7 8 9 10 11 12 13 Notes: 1 2 2 3 3 1. TRST is an asynchronous signal. The setup time is for test purposes only. 2. Non-test signal input timing with respect to TCK. 3. Non-test signal output timing with respect to TCK. Figure 5 provides the JTAG clock input timing diagram. 1 2 2 VM VM TCK 3 3 VM VM = Midpoint Voltage (1.4 V) Figure 5. JTAG Clock Input Timing Diagram PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 13 Freescale Semiconductor, Inc. Electrical and Thermal Characteristics Figure 6 provides the TRST timing diagram. TCK 4 VM TRST 5 Figure 6. TRST Timing Diagram Figure 7 provides the boundary-scan timing diagram. Freescale Semiconductor, Inc... TCK VM VM 6 7 Data Inputs 8 Input Data Valid Data Outputs 9 Output Data Valid Data Outputs 8 Data Outputs Output Data Valid Figure 7. Boundary-Scan Timing Diagram Figure 8 provides the test access port timing diagram. TCK VM 10 VM 11 TDI, TMS 12 Input Data Valid TDO 13 Output Data Valid TDO 12 TDO Output Data Valid Figure 8. Test Access Port Timing Diagram 14 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pin Assignments 1.5 Pin Assignments Part A of Figure 9 shows the pinout of the CBGA package as viewed from the top surface. Part B shows the side profile of the CBGA package to indicate the direction of the top surface view. The PBGA package has an identical pinout. Part C shows the side profile of the PBGA package to indicate the direction of the top surface view. Part A 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 A B C Freescale Semiconductor, Inc... D E F G H J K L M N P R T Not to Scale Part B Substrate Assembly Encapsulant View Die PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc. Pinout Listings Part C Substrate Assembly Mold Compound View Die Figure 9. Pinout of the CBGA & PBGA Packages as Viewed from the Top Surface Freescale Semiconductor, Inc... 1.6 Pinout Listings Table 11 provides the pinout listing for the 603e CBGA and PBGA packages. Table 11. Pinout Listing for the 255-Pin CBGA and PBGA Packages Signal Name A[0-31] Pin Number C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, GO2, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01 L02 K04 C01, B04, B03, B02 A04 J04 A10 L01 B06 E01 D08 A06 D07 B01, B05 J14 N01 H15 G04 Active High I/O I/O AACK ABB AP[0-3] APE ARTRY AVDD BG BR CI CKSTP_IN CKSTP_OUT CLK_OUT CSE[0-1] DBB DBG DBDIS DBWO Low Low High Low Low -- Low Low Low Low Low -- High Low Low Low Low Input I/O I/O Output I/O -- Input Output Output Input Output Output Output I/O Input Input Input 16 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Pinout Listings Table 11. Pinout Listing for the 255-Pin CBGA and PBGA Packages Signal Name DH[0-31] Pin Number P14, T16, R15, T15, R13, R12, P11, N11, R11,T12, T11, R10, P09, N09, T10, R09, T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04 M02, L03, N02, L04, R01, P02, M04, R02 A05 G16 F01 C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05, P12 A07 B15 D11 D12 B10 C13 B07, B08, C03, C06, C08, D05, D06, H04, J16 C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10, M12, P07, P10 A08, B09, A09, D09 D03 J03 D01 A16 B14 C09 H14 C02 A14 A02, A03 C11 Active High I/O I/O DL[0-31] High I/O DP[0-7] DPE DRTRY High Low Low Low -- I/O Output Input I/O -- Freescale Semiconductor, Inc... GBL GND HRESET INT L1_TSTCLK 1 L2_TSTCLK 1 LSSD_MODE 1 MCP NC (No-Connect) OVDD PLL_CFG[0-3] QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TC[0-1] TCK Low Low -- -- Low Low -- -- High Low Low Low Low Low -- Low High Low High -- Input Input Input Input Input Input -- -- Input Input Output Output Input Input Input Input Input I/O Output Input PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 17 Freescale Semiconductor, Inc. Package Descriptions Table 11. Pinout Listing for the 255-Pin CBGA and PBGA Packages Signal Name TDI TDO TEA TLBISYNC TMS TRST TS A11 A12 H13 C04 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D02 2 Pin Number Active High High Low Low High Low Low High High Low -- Low I/O Input Output Input Input Input Input I/O Output I/O Output -- Output Freescale Semiconductor, Inc... TSIZ[0-2] TT[0-4] WT VDD F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06, L08, L09, L11 F03 VOLTDETGND 3 Notes: 1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation. 2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core. 3. NC (no-connect) in the PID6-603e; internally tied to GND in the PID7v-603e and PID7t-603e CBGA and PBGA package to indicate to the power supply that a low-voltage processor is present. 1.7 Package Descriptions The following sections provide the CBGA and PBGA package parameters and the mechanical dimensions for the 603e. 1.7.1 CBGA Package Description The following sections provide the package parameters and mechanical dimensions for the CBGA package. 1.7.1.1 Package Parameters The package parameters are as provided in the following list. The package type is 21 mm x 21 mm, 255-lead ceramic ball grid array (CBGA). Package outline Interconnects Pitch Package height Ball diameter Maximum heat sink force 21 mm x 21 mm 255 1.27 mm (50 mil) Minimum: 2.45 mm Maximum: 3.00 mm 0.89 mm (35 mil) 10 lbs 18 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Package Descriptions 1.7.1.2 Mechanical Dimensions of the CBGA Package Figure 10 provides the mechanical dimensions and bottom surface nomenclature of the CBGA package. 2X 0.200 A1 CORNER A E T 0.150 T B P Freescale Semiconductor, Inc... 2X 0.200 F N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS DIM MIN MAX MIN MAX A T R P N M L K J H G F E D C B A INCHES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 21.000 BSC 21.000 BSC 2.450 0.820 3.000 0.930 0.827 BSC 0.827 BSC 0.097 0.032 0.118 0.036 B C D G K 1.270 BSC 0.790 0.990 0.050 BSC 0.031 0.039 H C H K N P 0.635 BSC 5.000 5.000 16.000 16.000 0.025 BSC 0.197 0.197 0.630 0.630 G 255X K D S S 0.300 0.150 TE T S F S Figure 10. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 19 Freescale Semiconductor, Inc. Package Descriptions 1.7.2 PBGA Package Description The following sections provide the package parameters and mechanical dimensions for the PBGA package. 1.7.2.1 Package Parameters The package parameters are as provided in the following list. The package type is 23 mm x 23 mm, 255-lead plastic ball grid array (PBGA). Package outline Interconnects Pitch Package height 23 mm x 23 mm 255 1.27 mm (50 mil) Minimum: 2.1 mm Maximum: 2.6 mm 0.76 mm (30 mil) 5 lbs Freescale Semiconductor, Inc... Ball diameter Maximum heat sink force 20 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Package Descriptions 1.7.2.2 Mechanical Dimensions of the PBGA Package Figure 11 shows the non-JEDEC package mechanical dimensions and bottom surface nomenclature of the the PBGA package. D D2 0.35 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 4. PRIMARY DATUM C AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS MIN MAX 2.10 2.60 0.50 0.70 1.10 1.20 0.50 0.70 0.60 0.90 23.00 BSC 19.05 REF 19.40 19.60 23.00 BSC 19.05 REF 19.40 19.60 1.27 BSC 256X 0.20 C A E E2 Freescale Semiconductor, Inc... 4X 0.20 A2 A3 A1 A C SEATING PLANE TOP VIEW B (D1) 15X DIM A A1 A2 A3 b D D1 D2 E E1 E2 e e T R P N M L K J H G F E D C B A SIDE VIEW 15X e (E1) 4X e /2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 256X b 0.30 M M CAB C BOTTOM VIEW 0.15 Figure 11. Package Dimensions for the Plastic Ball Grid Array (PBGA)Nnon-JEDEC Standard Note that Table 11 lists the pinout to this non-JEDEC standard in order to be consistent with the CBGA pinout. PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 21 Freescale Semiconductor, Inc. Package Descriptions Figure 12 shows the JEDEC package dimensions of the PBGA package. A D D2 0.35 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM C. 4. PRIMARY DATUM C AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS MIN MAX 2.10 2.60 0.50 0.70 1.10 1.20 0.50 0.70 0.60 0.90 23.00 BSC 19.05 REF 19.40 19.60 23.00 BSC 19.05 REF 19.40 19.60 1.27 BSC 256X 0.20 C E E2 Freescale Semiconductor, Inc... 4X 0.20 A2 A3 A1 A C SEATING PLANE TOP VIEW B (D1) 15X DIM A A1 A2 A3 b D D1 D2 E E1 E2 e e U T R P N M L K J H G F E D C B SIDE VIEW 15X e (E1) 4X e /2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 256X b 0.30 M M CAB C BOTTOM VIEW 0.15 CASE 1167-01 Figure 12. Package Dimensions for the Plastic Ball Grid Array (PBGA)NJEDEC Standard Note that the pin numberings shown in Figure 12 do not match Table 11 and the pinout of the non-JEDEC standard package (and the CBGA pinout) shown in Figure 11. Figure 11 should be used in conjunction with Table 11 for the complete pinout description. 22 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Design Information 1.8 System Design Information This section provides electrical and thermal design recommendations for successful application of the 603e. 1.8.1 PLL Conguration The 603e PLL is congured by the PLL_CFG[03] signals. For a given SYSCLK (bus) frequency, the PLL conguration signals set the internal CPU and VCO frequency of operation. The PLL conguration for the PID7t-603e is shown in Table 12 for nominal frequencies. Table 12. PLL Configuration CPU Frequency in MHz (VCO Frequency in MHz) PLL_CFG[0:3] Bus-to-Core Multiplier 2x 2x 2.5x 3x 3.5x 4x 4.5x 5x 5.5x 6x Core-to VCO Multiplier 2x 4x 2x 2x 2x 2x 2x 2x 2x 2x Bus Bus Bus Bus Bus Bus Bus 25 MHz 33.33 MHz 40 MHz 50 MHz 60 MHz 66.67 MHz 75 MHz -- -- -- -- -- -- -- -- -- 150 (300) -- -- -- -- -- -- 150 (300) 166 (333) 183 (366) 200 (400) -- 804 (320) -- -- -- 160 (320) 180 (360) 200 (400) 220 (440) 240 (480) -- 100 (400) -- 150 (300) 175 (350) 200 (400) 225 (450) 250 (500) 275 (550) 300 (600) -- 120 (480) 150 (300) 180 (360) 210 (420) 240 (480) 270 (540) 300 (600) -- -- -- 133 (532) 166 (333) 200 (400) 233 (466) 267 (533) 300 (600) -- -- -- 150 (300) 150 (600) 187 (375) 225 (450) 263 (525) 300 (600) -- -- -- -- Freescale Semiconductor, Inc... 0100 0101 0110 1000 1110 1010 0111 1011 1001 1101 0011 1111 PLL bypass Clock off Notes: 1. Some PLL configurations may select bus, CPU, or VCO frequencies which are not supported; see Section 1.4.2.1, "Clock AC Specifications," for valid SYSCLK and VCO frequencies. 2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 3. In clock-off mode, no clocking occurs inside the 603e regardless of the SYSCLK input. 4. 80 MHz operation is not supported for the PBGA package (see Table 7) PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 23 Freescale Semiconductor, Inc. System Design Information 1.8.2 PLL Power Supply Filtering The AVdd power signal is provided on the 603e to provide power to the clock generation phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be ltered using a circuit similar to the one shown in Figure 13. The circuit should be placed as close as possible to the AVdd pin to ensure it lters out as much noise as possible. The 0.1 F capacitor should be closest to the AVdd pin, followed by the 10 F capacitor, and nally the 10 W resistor to Vdd. These traces should be kept short and direct. 10 W Vdd 10 F 0.1 F AVdd Freescale Semiconductor, Inc... GND Figure 13. PLL Power Supply Filter Circuit 1.8.3 Decoupling Recommendations Due to the 603eOs dynamic power management feature, large address and data buses, and high operating frequencies, the 603e can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the 603e system, and the 603e itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each Vdd and OVdd pin of the 603e. It is also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should vary in value from 220 pF to 10 mF to provide both high- and low-frequency ltering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values for the Vdd pinsN220 pF (ceramic), 0.01 F (ceramic), and 0.1 F (ceramic). Suggested values for the OVdd pinsN0.01 F (ceramic), 0.1 F (ceramic), and 10 F (tantalum). Only SMT (surface mount technology) capacitors should be used to minimize lead inductance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitorsN100 F (AVX TPS tantalum) or 330 F (AVX TPS tantalum). 1.8.4 Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the 603e. 24 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Design Information 1.8.5 Pull-up Resistor Requirements The 603e requires high-resistive (weak: 10 KW) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 603e or other bus master. These signals areNTS, ABB, DBB, and ARTRY. In addition, the 603e has three open-drain style outputs that require pull-up resistors (weak or stronger: 4.7 KW10 KW) if they are used by the system. These signals areNAPE, DPE, and CKSTP_OUT. During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may oat in the high-impedance state for relatively long periods of time. Since the 603e must continually monitor these signals for snooping, this oat condition may cause excessive power draw by the input receivers on the 603e. It is recommended that these signals be pulled up through weak (10 KW) pull-up resistors or restored in some manner by the system. The snooped address and transfer attribute inputs areNA[031], AP[03], TT[04], TBST, and GBL. Freescale Semiconductor, Inc... The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. 1.8.6 Thermal Management Information This section provides thermal management information for the CBGA and PBGA packages for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level designNthe heat sink, airow and thermal interface material. Figure 14 shows the upper and lower limits of the die junction-to-ambient thermal resistance for both package styles. The lower limit is shown for the case of a densely populated printed-circuit board with high thermal loading of adjacent and neighboring components. PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 25 Freescale Semiconductor, Inc. System Design Information 40 35 30 25 Freescale Semiconductor, Inc... 20 15 10 Typical Upper Limit Typical Lower Limit 5 0 0 0.5 1 1.5 2 Air flow Velocit y ( m/ s ) Figure 14. Typical Die Junction-to-Ambient Thermal Resistance (21 mm CBGA and 23 mm WB-PBGA) To reduce the die-junction temperature, heat sinks may be attached to the package by several methodsNadhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (both CBGA and PGBA packages); see Figure 15. Caution: please note, when choosing a heat sink attachment method, any attachment mechanism should not degrade the package structural integrity and/or the package-to-board interconnect reliability. For additional general information, see this paper--Investigation of Heat Sink Attach Methodologies and the Effects on Package Structural Integrity and Interconnect Reliability. 26 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Design Information CBGA Package Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material Freescale Semiconductor, Inc... Printed-Circuit Board Option PBGA Package Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material Printed-Circuit Board Option Figure 15. Package Exploded Cross-Sectional View with Heat Sink PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 27 Freescale Semiconductor, Inc. System Design Information The board designer can choose between several types of heat sinks to place on the 603e. There are several commercially-available heat sinks for the 603e provided by the following vendors: Chip Coolers Inc. 333 Strawberry Field Rd. Warwick, RI 02887-6979 Internet: www.chipcoolers.com 800-227-0254 (USA/Canada) 401-739-7600 International Electronic Research Corporation (IERC)818-842-7277 135 W. Magnolia Blvd. Burbank, CA 91502 Internet: www.ctscorp.com Freescale Semiconductor, Inc... Thermalloy 2021 W. Valley View Lane Dallas, TX 75234-8993 Internet: www.thermalloy.com Wakeeld Engineering 100 Cummings Center, Suite 157H Beverly, MA 01915 Internet: www.wakeeld.com 972-243-4321 781-406-3000 Aavid Engineering 972-551-7330 250 Apache Trail Terrell, TX 75160 Internet: www.aavid.com Ultimately, the nal selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 1.8.6.1 Internal Package Conduction Resistance For this packaging technology the intrinsic thermal conduction resistance (shown in Table 3) versus the external thermal resistance paths are shown in Figure 16 for a package with an attached heat sink mounted to a printed-circuit board. 28 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Design Information External Resistance Radiation Convection Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads Printed-Circuit Board Freescale Semiconductor, Inc... Radiation External Resistance Convection (Note the internal versus external package resistance) Figure 16. Package with Heat Sink Mounted to a Printed-Circuit Board 1.8.6.2 Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 17 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, oroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease signicantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal interface material depends on many factorsNthermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 29 Freescale Semiconductor, Inc. System Design Information 2 Silicone Sheet (0.006 inch) Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease Specific Thermal Resistance (Kin2/W) 1.5 1 Freescale Semiconductor, Inc... 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi) Figure 17. Thermal Performance of Select Thermal Interface Material The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: Dow-Corning Corporation Dow-Corning Electronic Materials PO Box 0997 Midland, MI 48686-0997 Internet: www.dow.com Chomerics, Inc. 77 Dragon Court Woburn, MA 01888-4014 Internet: www.chomerics.com Thermagon Inc. 3256 West 25th Street Cleveland, OH 44109-1668 Internet: www.thermagon.com 800-248-2481 781-935-4850 888-246-9050 30 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. System Design Information Loctite Corporation 1001 Trout Brook Crossing Rocky Hill, CT 06067-3910 Internet: www.loctite.com 860-571-5100 1.8.6.3 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ta + Tr + (qjc + qint + qsa) * Pd Where: Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet qjc is the die junction-to-case thermal resistance qint is the adhesive or interface material thermal resistance qsa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation the die-junction temperatures (Tj) should be maintained less than the value specied in Table 3. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30 to 40 C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10 C. The thermal resistance of the thermal interface material (qint) is typically about 1 C/W. Assuming a Ta of 30 C, a Tr of 5 C a CBGA package qjc = 0.095, and a power consumption (Pd) of 3.0 Watts, the following expression for Tj is obtained: Die-junction temperature: Tj = 30 C + 5 C + (0.095 C/W + 1.0 C/W + Rsa) * 3.0 W For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (Rsa) versus airow velocity is shown in Figure 18. Freescale Semiconductor, Inc... PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 31 Freescale Semiconductor, Inc. System Design Information 8 7 Heat Sink Thermal Resistance (1/4C/W) Thermalloy #2328B Pin-fin Heat Sink (25 x28 x 15 mm) 6 5 4 Freescale Semiconductor, Inc... 3 2 1 0 0.5 1 1.5 2 2.5 3 3.5 Approach Air Velocity (m/s) Figure 18. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 7 C/W, thus Tj = 30C + 5C + (0.095 C/W +1.0 C/W + 7 C/W) * 3.0 W, resulting in a die-junction temperature of approximately 60 C which is well within the maximum operating temperature of the component. For a PBGA package, and assuming a Ta of 30 C, a Tr of 5 C a PBGA package qjc = 8, and a power consumption (Pd) of 3.0 Watts, the following expression for Tj is obtained: Die-junction temperature: Tj = 30 C + 5 C + (8 C/W + 1.0 C/W + Rsa) * 3.0 W Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 7 C/W, thus Tj = 30C + 5C + (8 C/W +1.0 C/W + 7 C/W) * 3.0 W, resulting in a die-junction temperature of approximately 83 C which is well within the maximum operating temperature of the component. Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakeeld Engineering, and Aavid Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air ow. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common gure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat ow. The nal die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level 32 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Ordering Information design and its operating conditions. In addition to the component's power consumption, a number of factors affect the nal operating die-junction temperatureNairow, board population (local heat ux of adjacent components), heat sink efciency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. To expedite system-level thermal analysis, several OcompactO thermal-package models are available within FLOTHERM. These are available upon request. 1.9 Ordering Information Freescale Semiconductor, Inc... Figure 19 provides the part numbering nomenclature for the PID7t-603e. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola sales ofce. In addition to the processor frequency, the part numbering scheme also consists of a part modier and application modier. The part modier indicates any enhancement(s) in the part from the original design. The application modier may specify special bus frequencies or application conditions. Each part number also contains a revision code. This refers to the die mask revision number and is specied in the part numbering scheme for identication purposes only. MPC 603 R RX XXX X X Product Code Part Identifier Part Modifier (R = Remapped, Enhanced, Low-Voltage) Package (RX = CBGA without Lid) (ZT = PBGA Package) Revision Level (Contact Motorola Sales Office) Application Modifier (L = Any Valid PLL Configuration) (T = Extended Termperature Range) Processor Frequency Figure 19. Part Number Key PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 33 Freescale Semiconductor, Inc. Ordering Information Freescale Semiconductor, Inc... 34 PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Ordering Information Freescale Semiconductor, Inc... PID7t-603e Hardware Specifications For More Information On This Product, Go to: www.freescale.com 35 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... DigitalDNA and Mfax are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Customer Focus Center: 1-800-521-6274 Mfax: RMFAX0@email.sps.mot.com Motorola Fax Back System HOME PAGE: http://motorola.com/semiconductors Document Comments: FAX (512) 895-2638, Attn: RISC Applications Engineering World Wide Web Addresses: http://www.motorola.com/PowerPC http://www.motorola.com/NetComm http://www.motorola.com/ColdFire - TOUCHTONE 1-602-244-6609 - US & Canada ONLY http://sps.motorola.com/mfax MPC603E7TEC/D For More Information On This Product, Go to: www.freescale.com |
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